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Walter Goodwin discusses placement, routing and experiment latency, arguing that faster AI assistance does not make every chip-design step instantaneous.
- 1Placement and routingSome design steps remain computationally expensive.
- 2Automation and latencyAutomating thought does not remove every delay.
- 3Experiment bottlenecksTesting still consumes time and resources.
ポイント
- Placement and routing can take substantial compute time.
- Some reasoning can be automated without eliminating all latency.
- Experiments still need time and resources.
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Chip-design latency
Fractile CEO Walter Goodwin discusses computationally expensive steps in chip design, including placement and routing.
Fractile CEO Walter Goodwin discusses computationally expensive steps in chip design, including placement and routing.
He says conventional layout tools can take days for a design, even if other parts of the work are assisted by AI.
Goodwin distinguishes automating some reasoning from removing the intrinsic latency of experiments or computational processes.
Experiments still take time
He draws an analogy to AI model development: better systems may guide experiments, but experiments still take resources and time.
He draws an analogy to AI model development: better systems may guide experiments, but experiments still take resources and time.
His point is that expensive design and validation steps can constrain the speed of progress, even when other tasks accelerate.
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