SemiAnalysis on ASML's Hybrid-Bonding Patents, HBM Economics and the Next Tool Ecosystem

Jordan Nanos opens the discussion with Howie and Sherry Zhang by explaining the claim behind SemiAnalysis's new article: ASML appears to be developing a hybrid-bonding tool. There has not been a product announcement. The evidence the team is discussing comes from patent filings it has annotated, and the purpose of the conversation is to examine what that design could mean.

Howie says a series of posts by a social-media account drew the team's attention to the patents, which had already been around for some time, including filings from 2025. The drawings suggested a distinctive way of applying ASML's existing capabilities to hybrid bonding. The researchers then investigated the conveyor arrangement and SuperTrak, comparing the proposed system with equipment already on the market.

The team does not expect this to happen immediately. Howie describes a development horizon of several years, but considers the design worth examining because it differs substantially from current tools. Sherry adds that SemiAnalysis has followed advanced packaging for years, including a series written by Dylan and colleagues in 2023 or earlier, so developments in this area attract sustained attention.

Howie begins with the conventional die-to-wafer arrangement. A base wafer remains in place while a pick-and-place mechanism takes individual top dies or chiplets, aligns them and places them on the target wafer. Other preparation and measurement steps happen before placement, and further processing, including annealing, follows. The particular tool under discussion performs the alignment and placement portion of that larger process.

In the ASML patent, the dies instead travel around a track or carousel. They pass through stations for operations such as measurement and plasma activation, then reach the bonding station. There, the wafer comes toward the die and meets it on the carrier. The reversal is the important idea: rather than repeatedly moving a die onto a stationary wafer, the system brings the wafer to the die.

That arrangement could let ASML use capabilities it already has in metrology and wafer-stage handling. Howie sees the patent as a way of translating those competencies into bonding. Jordan then asks whether the company might also be working on wafer-to-wafer bonding, and what distinguishes that approach from placing individual dies onto a wafer.

Sherry explains that wafer-to-wafer bonding joins two complete wafers, whereas die-to-wafer bonding starts with an individual die. The latter is more demanding in alignment, and the market still needs mature systems that deliver both the required accuracy and throughput. The researchers see reasons in the patent record to think ASML could pursue both approaches, but the stronger evidence concerns die-to-wafer development.

Sherry expects ASML to aim at the most advanced end of any market it enters, drawing a parallel with the position it holds in lithography. That expectation is part of the team's interpretation of the filings, rather than a confirmed product plan. Jordan asks how this prospective entrant compares with existing hybrid-bonding equipment suppliers such as BESI.

Howie describes companies such as BESI and ASMPT as coming from a pick-and-place background. Their expertise includes manipulating small chiplets with mechanical arms and precisely placing them on a base wafer. In the sequence he describes, placement itself does not apply force to create the final bond; the later anneal is part of completing the bonding process.

ASML approaches the problem from the front end of semiconductor manufacturing. Its lithography equipment operates with extremely fine overlay and alignment control when patterning transistors. As hybrid-bond pitches shrink and the number of signals between two dies becomes more important, that precision is potentially valuable. The task is to incorporate it into a system that handles dies and wafers in this different arrangement.

Howie calls the solution novel but stresses that translating an existing capability into a new tool creates implementation challenges. Jordan connects the discussion to the team's earlier work on hybrid bonding and AMD's 3D V-Cache, then asks about a striking forecast in the new research: HBM is not expected to adopt die-to-wafer hybrid bonding before 2029, if it adopts it at all.

Howie sees logic as hybrid bonding's primary use case. Functional units that would otherwise sit side by side can be divided across two vertically adjacent layers. The connections between them become shorter, and more wires can run between the layers. That changes the communication limits that would apply if the same functions occupied neighboring regions on one die.

He holds up a Huawei handset that he describes as the XT2 with a 9050 chip. In the team's account, it uses two hybrid-bonded silicon layers to divide functional blocks and make better use of the process technology available to it. The benefits they emphasize are power efficiency and a larger effective area budget within the physical constraints of a phone.

HBM presents a different problem. Howie describes hybrid bonding there mainly as a way to put more memory layers within a limited thickness, citing a ceiling around 775 microns and a possible best-case capacity increase of about 50% per stack. Memory vendors have invested research and marketing effort in the approach, but he argues that the return on that investment is not yet compelling.

Hybrid bonding is more expensive to implement than the reflow or thermocompression bonding processes used for HBM. It may provide some improvement in thermal behavior or signal integrity, but the main attraction is greater stack density. Howie says that is not currently the top priority in many customer requests: for a given performance and bandwidth target, some buyers are asking vendors to reduce the number of layers instead.

If an HBM design does not need hybrid bonding to meet its requirements, Howie sees little reason to incur the extra cost. That is why the team does not expect high-volume adoption soon and instead focuses on logic as the nearer-term use case. Sherry adds that the economics of how many layers to stack, together with alignment and throughput challenges, underpin their 2029-or-later adoption estimate.

Jordan notes that an ASML roadmap from 2024 shows hybrid bonding appearing across NAND and DRAM, which looks more optimistic than the researchers' assessment. Howie replies that equipment vendors have an incentive to anticipate complex new processes because those processes create demand for tools. He recalls optimistic transistor-density projections in earlier High-NA material and recommends treating such roadmaps cautiously.

Returning to the annotated patent drawing, Sherry contrasts conventional stationary chambers with ASML's track arrangement. In existing flows, dies move between tools and are processed at each station. The proposed design instead carries each die through the sequence on its own holder, changing which parts of the production system need to move.

The patent names SuperTrak Conveyance as a potential supplier of the track. Sherry contrasts the design with a BESI-style flow in which a bond head picks up a die prepared elsewhere. In ASML's arrangement, the die stays on its individual holder as the carrier moves between stations, leaving only when the bonding step takes place.

Howie emphasizes why keeping the die on that carrier matters. The exact orientation in which it was initially placed can be measured by later stations, and the system can compensate for that orientation at bonding. Instead of transferring the die each time, the equipment must approach it: individual chambers or functions come down toward the carrier, and eventually the wafer does the same.

That creates a new equipment-design problem. A metrology system that normally measures in a stationary arrangement now has to engage with a die on the conveyor. The unusual form factor may require co-design agreements with suppliers of pre-bonding functions so their equipment can operate within the track system. ASML could also build some of those functions itself, particularly in metrology.

The remaining question is whether measurement accuracy can be preserved as the equipment itself moves into position. Howie identifies cleanliness as another major challenge. The track could extend for several meters and expose several square meters of area. The system needs a way to control the environment while a die moves between stations and while equipment approaches and encloses it.

Jordan asks the researchers to separate two requirements: alignment accuracy and cleanliness. A single particle between the surfaces can leave an area unbonded and create a defective result. Howie first explains alignment as measuring the true location of the bond pads, then adjusting the relative positions of the die and wafer before they meet.

Those adjustments go beyond translation in X and Y. The system must also account for rotation and out-of-plane tilt, giving six degrees of freedom to consider. Measurable structures on the die reveal its orientation on the carrier, while features on the wafer establish its position in space. The surfaces must approach each other vertically with their bonding features correctly overlaid.

Cleanliness is distinct from alignment. Howie explains that hybrid bonding requires very flat, particle-free surfaces. The dielectric surfaces bond, and a subsequent anneal heats the structure so the copper expands to fill the remaining gap. A particle caught between the layers does more than spoil a single connection: it can hold the surfaces apart over a much larger region.

He compares contamination to a wedge that prevents the surrounding surfaces from meeting. A die that is clean at one station must still be clean when it arrives at the next. Sherry adds that alignment and cleanliness together determine bonding yield. A useful production tool needs both a high share of successful bonds and sufficient throughput, which makes the process resemble front-end manufacturing in its demands.

Sherry connects those demanding requirements to the increasing participation of front-end equipment companies. ASML is not the only one looking at the area. She also sees particular importance for China, where advanced packaging can offer another route to scaling under limits on process technology. Suppliers such as NAURA and AMEC are expanding capabilities through acquisitions or investment.

Jordan asks how bonding can help when further shrinking a logic node is constrained. Howie begins with a simple tradeoff: more silicon operated at a lower voltage can sometimes deliver better efficiency within a given power envelope. Hybrid bonding takes that idea further by placing two silicon layers close together and giving them many direct connections. It offers another path to performance improvement when process options are limited.

A more specific benefit comes from how the logic is partitioned. Howie describes moving less timing-critical functions, such as SRAM memory cells, to another layer. That clears space so high-speed functional units within a core can sit closer together. Shorter connections reduce timing delay and routing congestion. In the Huawei example, he cites clock speeds up to 2.7 GHz without a corresponding increase in voltage or power.

At a more general level, using a larger silicon-area budget for the same architecture and power limit can improve efficiency by enabling lower-voltage operation. Howie also connects lower voltage with reduced leakage and less wasted power in moving signals. These are the kinds of gains the team sees making hybrid bonding valuable even when it does not come with a more advanced lithography process.

Jordan asks Sherry whether China's opportunity implies that hybrid-bonding equipment avoids export restrictions or that domestic suppliers could build it. She does not treat those as settled policy questions. International incumbents still dominate: she identifies BESI with die-to-wafer systems and mentions EVG and ASMPT among suppliers in wafer-to-wafer bonding. Chinese equipment companies are nevertheless building their capabilities.

Sherry describes geopolitical uncertainty as an incentive to develop a domestic supply chain, much as it has been for other semiconductor tools. Howie sees the ambition in technical roadmaps as well. In data-center accelerators, Chinese developers are working to overcome power-density limits and are aiming for extensive hybrid-bonded logic folding around 2030.

Howie says some of those plans target tighter bonding pitches than TSMC's SoIC and envisage three layers rather than the two-layer structures discussed earlier. Additional layers can reduce yield, which would mean more equipment capacity is needed to produce the same quantity of working output. The ambition of those roadmaps therefore has implications for both technical development and demand for tools.

Jordan changes topic to another long-term initiative: ASML and foundries including TSMC, Intel's foundry business and Samsung discussing larger photomasks for High-NA EUV. He asks what the change enables and why it is not imminent. The issue, Howie explains, starts with the smaller exposure field imposed by High-NA's optical arrangement.

The anamorphic optics reduce the mask pattern eightfold in one direction and fourfold in the other. That effectively halves the maximum field, leaving a maximum die area of roughly 400 square millimeters compared with about 850 square millimeters in the current full-field arrangement. Designers who want a larger chip must account for that constraint rather than assume the old field remains available.

One interim approach is stitching. Howie describes reserving regions in the chip floorplan where the design accommodates an exposure boundary, potentially using other layers that are not printed with High-NA to connect across it. The approach can work, but it puts extra constraints on design and requires the boundary to be considered explicitly.

A larger mask offers another route. Around the 2030 timeframe, the researchers discuss a format commonly described as six by twelve inches, doubling the length in one dimension. After the different reduction factors in each axis, that could restore the full exposure field. It would ease design constraints and improve throughput, extending ASML's high-productivity tool direction.

Sherry points out that the change extends well beyond ASML. Mask makers and the rest of the supply chain must adapt, so coordination with fabs takes time. The move cannot be delivered simply by altering one piece of exposure equipment while leaving every upstream and supporting process unchanged.

Throughput also affects equipment economics. Sherry refers to ASML management's description of value-based pricing: when a tool produces more output, the value it creates can support a higher price. In her view, larger masks and higher productivity could therefore matter commercially as well as technically over the longer term.

Asked what must change in the supply chain, Howie lists mask production, inspection, protective pellicles and repair. Even the nominal dimensions involve practical compromises: he says the longer side is closer to 11.2 inches than a literal twelve, helping the blank fit within existing material-handling constraints while leaving enough space for the larger pattern.

Carriers, overhead handling equipment and the way masks are protected all need consideration. A larger patterned area also makes electron-beam inspection, metrology and repair more complex. Howie compares the level of coordination to the industry's move from eight-inch to twelve-inch wafers in the early 2000s. Foundries and ASML need to commit early enough for suppliers to develop the ecosystem together.

Jordan asks whether these developments could deepen a split between manufacturing ecosystems: one pushed toward hybrid bonding under process constraints, another continuing to shrink features with High-NA and larger masks. He also wonders whether returning to a larger exposure field makes designs more transferable, while acknowledging that the two approaches may still demand very different design flows.

Howie says divergence is already visible in EDA. Designing several silicon layers requires choices about which functions belong on each layer. He describes Huawei working with design companies on that partitioning. It is a different problem from the simpler separation associated with AMD's use of SoIC, where CPU cores and L3 cache occupy distinct layers.

Logic folding can split functions within a core itself. Howie names smaller elements such as multipliers and buffers as examples of components that may be distributed across layers. That requires a more detailed multi-layer design flow than simply stacking a cache die. He argues that those requirements are already pushing the development of tools that differ from established Western EDA workflows.

Sherry turns to manufacturing and supply chains. She does not claim expertise in predicting future policy, but describes what the team sees from Chinese companies: domestic substitution is moving from a predominantly state-led initiative toward more coordinated work between equipment makers and fabs. They are designing equipment and EDA capabilities together from the ground up, in response to needs that can differ from the rest of the world.

In Sherry's assessment, those efforts are unlikely to disappear as export-control policies change. Restrictions can instead strengthen the motivation to localize the supply chain, as she believes recent experience in Chinese semiconductor equipment has shown. Her point is about the direction and coordination of work on the ground, rather than a forecast of a specific policy decision.

As the conversation closes, Jordan identifies a question still worth asking: what ASML must demonstrate as it develops the proposed bonder. The episode does not provide that detailed assessment because the team has reserved it for its paid research. The guests point toward future work, including a Huawei-phone teardown, rather than presenting the patent design as a completed production solution.

Sherry closes by describing the steep learning curve of working on these technical supply-chain questions with her colleagues. She hopes readers find the technical research useful and says the team will continue updating its work on ASML and other parts of the equipment ecosystem. The conversation ends with development questions still open and further reporting to come.