Dwarkesh Patel: What will computer chips look like in 2045?

There has never been a shock to the semiconductor industry like the current surge in demand from AI. Gary Dickerson says AI is driving incredible computing demand. Peter Wennink puts it at easily 40 to 50 percent above maximum capacity, something he had never seen. Progress in AI has been driven by exponentially increasing compute. To keep that going, foundries like Intel will need far more leading-edge silicon — both more chips and better chips.

Production of those chips is bottlenecked by tools Intel buys from its suppliers, most famously ASML’s EUV machines. A news clip puts it bluntly: without the equipment, they cannot make the chips here. Dwarkesh Patel spent two days touring Intel’s fabs to prepare for interviews with its leadership. He wanted to understand what it takes to manufacture the world’s most advanced chips, and how hardware is shaping the future of AI.

Dwarkesh sits down with Chris Auth, who leads development of all the processes currently under manufacturing. He wants the concrete version of how a new process happens. If 14A is two or three years from shipping, what is happening between now and then? How is yield improving, what telemetry do they look at, what experiments do they run?

Auth says 14A has already been in development for about three-plus years, so a lot of pre-work is done. They are close to finalizing the process and the tool sets it will run on, and they are fine-tuning each step. There are about 2,000 steps in the factory. Each one has to be intricate enough to go into manufacturing, run thousands of wafers a week, and be repeatable every single time.

Dwarkesh asks how yield actually rises month over month on a 14A line: how they find defects and how they fix them. Auth describes a constant loop. Inline metrology tools look at wafers and flag defects as they happen. At the end of the line they use electrical test or sort to see where chips fail, then analyze those failures.

They cross-section the fail — Dwarkesh was in the TEM lab the day before. From a cross-section you can see which layers the defect sits between, which section of the flow it came from, and whether inline metrology in that section already saw the same defects. Those are the ones you go after.

The lesson, Auth says, is that you do not want too much innovation in one node. More invention makes the process more complex. You can get it to work, but you still have to hit the schedule the customer wants. Predictable schedule is the key piece: figure out how much innovation you can put in and still meet the customer’s timeline.

Intel learned how costly that tradeoff can be on 10nm. The original target launch was 2016; manufacturing did not start until 2018. Analyst Vivek Arya notes that Intel had been the keeper of Moore’s Law, a new cadence every two years, but that last set of products slipped almost four years. A Yahoo Finance clip from the time: Intel’s worst day in four months, the stock down more than 15 percent, TSMC up 13 percent on the news.

Dwarkesh asks what lessons Intel took from 10nm. Auth says it was a case of very aggressive targets. They were doing what they called hyperscaling — shrinking much faster than history — and they invented around the fact that the new tools were not ready. That put a lot of burden on the process and on the engineers.

In the end, 10nm is a great technology: world-class yield, performance, and cost. It just took longer than they wanted. They have tried to take that into later nodes: limit the amount of innovation you put in so you stay on schedule. Asked what should have been saved for a future version, Auth says EUV was probably the big thing. When they defined 10nm, the conclusion was that EUV was not ready.

EUV is extreme ultraviolet lithography. It prints chip patterns with light at 13.5 nanometers, about 14 times shorter than the 193 nm tools chipmakers had used. The shorter the wavelength, the finer the features a single exposure can print. Intel decided the technology would not be ready in time.

TSMC moved sooner. It put EUV into volume manufacturing in 2019 and ramped it further on 5nm in 2020. Intel’s first EUV process did not reach products until 2023, so TSMC had about four more years of experience with the machines.

Dwarkesh asks how they decide whether a research idea — 2D materials, CFET, ruthenium interconnects — is mature enough for the next node. Auth says 10nm also produced a set of maturity metrics used in a process they call phase gate: yield, defect, and performance criteria to go from pathfinding into development. Miss them and the idea slips to the next technology. They focus on what is ready, because staying on schedule is the key thing.

Staying on schedule is hard partly because new transistor designs take decades to mature. Modern chip transistors evolved from the planar MOS transistor, demonstrated in 1960. The history since has been a climb from two dimensions into three. Each step Auth will describe, from FinFET to gate-all-around, is a step in that progression. It helps to start with a basic transistor and how its parts changed.

A transistor is a switch. When it is on, current flows between two ends called the source and the drain. A gate sits on top of the silicon between them. A positive voltage on the gate turns the switch on because it pulls negatively charged electrons in the silicon up toward the gate. A thin layer of insulation stops them from actually reaching it, so they collect just beneath and form a thin conducting path from source to drain: the channel. Remove the voltage and the electrons disperse, the channel disappears, and the switch turns off.

As transistors shrank, source and drain got so close that current could flow through the channel even when the switch was supposed to be off. They needed a better way to control the channel and stop leakage. The fix was to give the gate a tighter grip by touching the channel from more sides.

In the original planar transistor, the gate only touches the channel from the top. The FinFET squeezes the channel into a thin vertical fin of silicon. The gate drapes over the fin, so it controls the channel from three sides. The next step was to cover the bottom as well. Gate-all-around slices the channel into thin ribbons, each of which gets completely wrapped by the gate.

Getting that to work required new materials and new manufacturing steps. To build floating ribbons of silicon, you first sandwich them between alternating layers of a temporary placeholder that holds the space where the gate will eventually go. The real gate materials would not survive the processing that comes after, which involves baking the wafer at around 1,000°C.

Once the hot steps are done, chipmakers etch away the placeholder, leaving the ribbons suspended. They fill the gaps around every ribbon with a thin coat of a high-k insulator, whose job is to let the gate pull more strongly on the channel, and then put the metal of the gate on top of that.

FinFET was demonstrated in a lab in 1989 and reached volume production at Intel in 2011. A gate-all-around transistor had been demonstrated a year earlier, in 1988, but Samsung did not begin producing gate-all-around chips until 2022. The ideas were developed around the same time and reached production a decade apart. Dwarkesh wanted to know why gate-all-around took so long.

He asks Auth to walk through high-volume manufacturing: once you have the idea of a smaller, surrounded channel, how do the materials-science problems — including not destroying the gate — actually get figured out, and why does it take so long? Auth says they knew the idea in the 1990s, and they knew the manufacturing problems. At the same time they had high-k metal gate, strained silicon, and FinFETs. You do not tackle something before you have to. If those other knobs still drive performance, you use them.

They went through strained silicon, high-k metal gate, FinFETs, and then it became: we need to go further. Gate-all-around is really the ultimate transistor; maybe it is time to tackle those issues, including how you put high-k metal gate together with it. That invention takes time. Sometimes you need new materials. Sometimes you need a different tool, which means asking a vendor for a tool that can do X, a gas that deposits this material, a heating chuck with this characteristic.

All of that takes time, and some of it is iterative: run a gate-all-around transistor, see that it did not work, figure out what was wrong with the hypothesis, try a different structure. Dwarkesh asks how R&D itself changed from the Dennard-scaling era of just making planar transistors smaller to a world where size improvements do not come as easily and you have to work many facets of performance at once.

Auth says the 1980s and 1990s were driven by Dennard scaling and lithography: make things smaller, transistors get faster and more reliable, a predictable cadence. In the 2000s that was not good enough. For him it became a golden age of innovation. Each node had to answer how you provide more scaling and more performance. That drove strained silicon, high-k metal gate, FinFETs, gate-all-around, backside power — things you would not have touched in the 1980s because you just kept scaling the same flow.

For a transistor junkie, he says, it is awesome: the playbook is open. You can bring in new materials. The number of materials they use has probably gone up 10× since the 1990s. Atomic layer deposition means you are controlling this stuff atom by atom. Before, the approach was try not to change anything. Now it is take the sledgehammer, tear the thing up, and come up with a new idea.

For 14A, Intel is using a new kind of lithography machine: High-NA EUV. It uses the same extreme ultraviolet light as today’s EUV tools, but changes the optics. NA, or numerical aperture, measures how wide a cone of light the machine’s mirrors can focus onto the wafer. The wider the cone, the smaller the spot your light can carve. Standard EUV has an NA of 0.33. High-NA widens it to 0.55, so it can print features about 1.7 times smaller in a single pass.

When features are smaller than the machine can print, chipmakers split the pattern across several passes, each printing a different set of features. The tightest patterns can take two, three, or even four passes. Each extra pass eats time on a machine that costs around $200 million and adds another chance for defects. High-NA machines cost about twice as much, but they can cut the number of passes. Whether they justify the price is a question of time saved and defects avoided.

Dwarkesh asks why Intel is using High-NA for 14A when TSMC has said it does not make economic sense yet. Auth says it is a good example of how architecture changes the conclusion from the same tool set. Intel uses backside power, which alleviates some of the pitch requirements on the front side, so they can print that directly with High-NA. TSMC has to run tighter pitches because they do not have backside power, and they cannot do that with High-NA, so they have to use double-patterning EUV. For them it is not very helpful; for Intel it is.

At 14A they have left High-NA as an option, something they will discuss with the customer, because there is a value proposition and some complexity. Dwarkesh then explains backside power. A chip has two kinds of wiring. Power lines deliver electricity and need to be thick. Signal lines let transistors talk to each other; they are thinner, but they need space so one wire’s signal does not interfere with another’s.

In the past, all of those power lines and signal lines had to be crammed together on top of the transistors. Intel’s newest process moves the power lines below the transistors, to the back of the wafer. That frees space on top, so the signal lines do not have to be packed as tightly. Without backside power, the wiring is so tight it would still need multiple passes even with High-NA. With backside power, a single High-NA pass is enough.

Outside companies can now commission Intel to manufacture chips they have designed. They follow Intel’s process design kit, or PDK: the menu of what a given process can build and the rules for building it. Dwarkesh asks whether High-NA has to be locked into the PDK now for customers planning 14A. Auth says it is an option today, handled customer by customer.

On 18A, there was public reporting of PDK delays and instructions that did not work, which made it hard for people to use Intel as a foundry. Dwarkesh asks about becoming a foundry and having a PDK other customers can use. Auth says there is a learning curve, and competitors went through it too. For decades Intel was an IDM: they showed transistor data to their own product teams and never had a formal PDK process. That is new on 18A, which started without one.

They have taken a lot of customer feedback on what quality and maturity they expect in a PDK and what information they want to see. 14A will have high-quality PDKs from the get-go. There are maturity metrics for a PDK 0.5 versus 0.9 versus 1.0, and they keep incorporating feedback. Dwarkesh notes that for most of its history Intel’s fabs made only Intel’s chips, which may have helped TSMC: serving many customers gave TSMC more wafers to learn from, more revenue to reinvest, and more pressure to hit deadlines.

Dwarkesh asks a counterfactual. If a butterfly flapped its wings in the 1960s, could they imagine a world where gate-all-around is not even a word, and people went down a completely different branch of the tech tree? How far down could things be totally different? Could they not even be using copper?

Auth thinks the transistor path to gate-all-around as the ideal structure was somewhat inevitable; they were already talking about it in the 1990s. Backside power is more out there. Even in the 1990s, the idea that you would strip off the entire silicon substrate and put lines on the back was a stretch. Copper wires are the best, so he does not know how you would end up somewhere else — except that for the very tightest pitches it is inevitable you will replace copper. For the larger lines, copper is about where it is at.

Once you do gate-all-around and backside power, you enter a different regime. It is no longer a substrate with everything stacked on top. You have a transistor floating in interconnect, and you start asking: why not transistors, interconnect, more transistors, more interconnect? The 3D stacking they already do with discrete chips sitting on each other makes you ask why you cannot just build an entire structure like that.

You already see it in memory. NAND has incredible 3D structures; DRAM talks about it and Auth thinks DRAM will go there too. A lot of people say they will not do this because they cannot do it in the next five years. Put a larger timescale on it: 10 years, 20 years, 2045. Then you can see pretty exotic structures. They limit themselves by what looks possible in the next four years. Ask about scaling and they have visibility for about four years; get there and they can see another four. Talk about 10 years and it becomes hard to say.

Chris’s idea of building upward could start with the transistors themselves. Chips use two types, n-type and p-type, which work the same way with the charges reversed. Nearly every circuit pairs them. Today they sit side by side. The next step is to stack them directly on top of each other to save space. In principle that fits twice as many transistors in the same area. The design is called a CFET, complementary field-effect transistor. Every extra layer adds manufacturing steps and cost, and heat that does not have a clear way to escape.

Dwarkesh asks whether heat is the fundamental long-run issue: logic consumes more power than memory, so you cannot stack logic the way you stack DRAM into HBM or 3D NAND. Auth says three things limit compute: how fast you can switch (frequency), how much power that switch takes (efficiency), and how you dissipate the heat the switch generated (thermals). These are not new problems; you can find articles from 20 years ago. Thermals get harder with 3D devices. System-level analysis and simulation tools are in their infancy. It is a limiter and will be, but these are problems they can solve.

The problems respond to work, but engineering time is finite, and so are the wafers for experiments. Deciding where they go across thousands of problems is itself one of the hardest parts of bringing up a node. Dwarkesh sat in on one of Intel’s Hot Topics meetings, where those decisions get made. He is with Kevin Fischer, who was laying down the law that morning on how they are improving 18A and 18A-P. People came with experiments and ideas for yield and performance; Fischer and the integration engineers told them what data they needed and how to move faster.

Dwarkesh wants a sense of the culture. This meeting is bottlenecking Intel’s most advanced node. They want progress fast, so Fischer lays down the hammer. Fischer says the average engineer does not understand the stakes: how this hits Intel’s bottom line and the customer. They have no visibility. They hit a boundary — someone said no — and they are done. One thing you learn in this industry is that you will never have a complete data set. If you wait for one, you have waited too long.

A lot of what Fischer does in those meetings is decide how much risk to take. Do we go now? Do we start risking production? You are risking the bottom line. You are risking revenue. He worries Dwarkesh will make him look like an ogre for putting the hammer down. Dwarkesh says that is a great reputation to have. Fischer says it is really conveying urgency. Every day counts.

Asked for a particular issue, Fischer points to epi nodules from that morning. Epi is short for epitaxy: growing new material on an existing one. Chipmakers flow gases over a heated wafer; the gases leave atoms on the surface. The crystal underneath acts as a template, so each new atom lines up with the ones below. They use epitaxy at several stages. In the step Fischer describes, they grow the source and the drain as small crystals on either side of the gate.

During that deposition they get abnormal growth, a little thing like a tumor, growing super fast. One epi shorts to the wrong epi and transistors stop working. Then you have to narrow down how you will fix it. After the sponsor break, Fischer continues: that morning they were looking at a special clean that would eliminate the nodule after it deposited. Other discussion was about getting rid of the source of the nodule.

Dwarkesh asks how they decide what the source is. Fischer says they work highly in parallel. It is not always evident what the easiest fix is, so they work all the potential fixes, and sometimes it is not the one they expected first. Once they have identified it as a primary problem for the technology, the Hot Topics meeting aligns resources into those engineering teams so they can accelerate.

Dwarkesh asks about a fast-track so wafers can move faster if they are bottlenecking an experiment. Fischer describes a tiered system of hot boxes in the factory. Every grade goes a little faster; it is how the factory prioritizes that lot of silicon. The highest grade, HotBox 1, races through and gets priority at every tool, but it is a drag on the entire factory. Factory people do not like playing that card, because you use the tools inefficiently to go super fast. Think of a highway with one lane set aside for that one experiment. Everyone else clears out, and that lot races down.

Kevin’s job is deciding what goes onto the production line now. The day before, Dwarkesh went to Intel’s research lab with Jack Kavalieros to see ideas that are not ready for the node yet. They started with wiring. A transistor is only useful once it is connected to others, and on a modern chip that takes more than a dozen layers of metal wire stacked above the transistors, called interconnect. Those wires are copper, and as they shrink, copper starts to run into trouble. Intel is exploring a replacement: ruthenium.

Dwarkesh asks why they would explore ruthenium when it has higher resistivity. Kavalieros says that as you scale copper wires you run into challenges. Copper typically needs a liner in order to deposit and fill the lines. Ruthenium is different because it is a material they can etch, so they do not need that liner. Scale to very fine dimensions, trade off a resistive liner for no liner, and ruthenium starts to win.

There is a crossover where ruthenium has much better conductivity — better resistivity — than copper, roughly in the 20-nanometer pitch range. Half of that pitch is the metal line; the other half is the dielectric that isolates them. The liner, Kavalieros says, is almost a glue or transition layer so copper will stick and connect to the copper lines below. These are interlocking copper lines. Every time you deposit copper you have had a liner underneath. In the past that liner could be a significant share of the whole conduction path. They have scaled it thinner, and copper came back as a contender.

Dwarkesh asks how they decide a technology is mature enough for high-volume manufacturing. At 10nm they moved from copper to cobalt and there were issues. Kavalieros says integrating these materials into the transistor ecosystem involves many components. Scalability is one part; ability to integrate is another. When they chose cobalt it was the forerunner, and the results were stronger at the time.

As they work with the vendor ecosystem that provides materials and tools, they find solutions down the road that may bring copper back in line as the stronger of the two. That is exactly what happens. Every technology, they evaluate multiple options. As they get closer to the horizon for a manufacturing-worthy product, they have to decide. The leading option at the time was cobalt. Now it is copper again. Perhaps in the future it will be ruthenium.

Dwarkesh wants Kavalieros’s thoughts on CFET: stacking transistors on top of each other. What is progress like? Can they keep adding layers — two, three, four — how high can they get? Kavalieros says the evaluation is underway, not just at Intel but at competitors and external labs. It is the ultimate in stackability. They are taking transistors that had to be compressed more and more and relaxing that by stacking them.

Stacking does not mean they are not interconnected. What used to be connections on the top or even the bottom now has to go vertically between the transistors. That is a new challenge: the aspect ratio of creating trenches and filling them gets harder. It is not as straightforward as stacking the devices, because you still have to think about wiring them. Dwarkesh asks if the issue is the etch to get that deep hole. Aspect ratio for the etches is a big part, Kavalieros says, and they are working with vendors on it. It is also what you fill those tiny spaces with. Filling can leave air gaps or holes that never really fill, and that is not ideal.

Dwarkesh assumes there is a version of CFET that works in this lab. What wafer or process is working now, and what are the next steps until it is in a full high-volume flow? Kavalieros says evolving an architecture, not just a chemistry or a material, means they have to make short-loop vehicles for faster turnaround. The normal manufacturing process can take a month or longer to complete the thousands of steps. The goal here is to take unit cells of that process and qualify them.

Short-loop vehicles give electrical and chemical parameters that resolve speed bumps. Once those are resolved, they combine them into a more complex test vehicle. In here you might be making something very simple: a diode, a capacitor, components of the transistor. As those get stronger, you combine them into the transistor itself. For CFET they might not do four ribbons on four ribbons. They might do one on one, because the aspect ratio of something that much taller is more challenging. A simplified CFET with one wire for NMOS and one for PMOS still lets them evaluate stacking and interconnect.

Are the feature sizes here as small as they will eventually be, or bigger? In some cases at least as small, Kavalieros says. 2D materials — transition-metal dichalcogenides — are essentially one monolayer of atoms. Those depositions can happen in this lab. They can evaluate conductivity, contacting, and modulating that conductivity, which is what the transistor does. They can deposit films thin to the atomic scale and print very small features with EUV or e-beam, similar to what they will eventually make in production.

Dwarkesh still does not intuitively get it. If they already have a working CFET at production-like feature sizes, why will it take 10 years to be in a phone? Kavalieros says the answer is slightly different for an architecture like CFET versus a novel material. Materials have to be deposited, etched, removed, and proven compatible with layers above and below before you put them in a production line. An architecture may look like a simple evolution — you are already making nanoribbon transistors next to each other, what is wrong with stacking them? — but stacking increases the aspect ratio for etches, depositions, and cleans, and the technology may simply not be ready yet.

If they have already made it here, is there not a version of the technology that is ready? Correct, Kavalieros says. They have made a simplified version that may not be an advantage over the current side-by-side nanoribbons. They need to evolve it to maybe two nanoribbons, or add the right metals and dielectrics, to extract the maximum performance. There are a thousand different steps that all have to come together in a unique way to make the performance compatible with, or actually better than, the prior technology.

Where do ideas tend to fail? You have 20 ideas like 2D materials; how do they decide one is not worth pursuing? Sometimes they discover fundamentals that are incompatible with the rest of the process. First experiments may be simple depositions: I can deposit the film, look at it, measure it. The moment I try to make a contact, nothing sticks. Adhesion of the next step can rule a material out.

More complex failures are gaseous interactions with downstream steps. You deposit the film, cap it with other materials, but they are not hermetic, so the third, fourth, or fifth step still interacts with it and changes its properties. That makes it unstable, and now you have to find better hermetic sealing. If you cannot control it, it is a dead end.

Stacking transistors remains a research problem, but stacking complete chips is already in production. It addresses how separate chips communicate. Patel uses Nvidia’s Blackwell data-center GPU as an example: two large processor chips surrounded by eight stacks of high-bandwidth memory must continually exchange data. In AI workloads, moving that data can limit completion time more than the amount of raw computation available.

There is a geometric mismatch between computation and communication. Imagine neighboring chips exchanging data along their facing edges. Double each chip’s width and length, and the area available for circuitry increases fourfold while the edge available for connections only doubles. Denser transistors intensify the imbalance: the ability to compute can grow faster than the ability to move the resulting data.

Packaging connects a finished chip to other chips and the rest of the computer. Patel sketches its evolution from side-by-side chips with connections leaving their edges to multiple chips sitting on a shared piece of silicon, an interposer. Wiring through the interposer gives them more communication density. This arrangement is commonly called 2.5D packaging.

Bonding chips directly together is another route to shorter, denser connections. Early versions used solder bumps, which occupy space and add resistance. Hybrid bonding removes the solder and joins the chips’ signal connections directly. It has become a major area of industry investment because the interface can be much denser than a bump-based connection.

The process aligns the copper interconnects on two surfaces, brings them together, and applies heat so the copper expands to bridge the gap. The surrounding insulating surfaces bond too. Achieving this in volume required solving alignment and defect problems. In Intel’s packaging lab, Patel asks Tyler Osborn, a director in advanced packaging technology development, how the approach works in practice.

Patel asks about alternative bonding approaches. Osborn clarifies that bonding two complete wafers is generally called wafer-to-wafer at Intel. It is already widely used for CMOS image sensors, and researchers are exploring applications such as memory stacking. But the geometry of the dies on the two wafers must match, with corresponding locations able to align directly.

Yield creates a second difficulty for wafer-to-wafer bonding. Good dies on one wafer will not generally align perfectly with good dies on the other. Some good devices inevitably bond to defective partners, wasting usable silicon. If the patterns of good and bad dies matched exactly, that loss could disappear, but Osborn says the odds of such a perfect match are very low.

Chip-to-wafer bonding gives Intel more control. Individual dies can be separated and tested, then known-good chips placed only on known-good positions of the base wafer. Osborn expects both approaches to remain available because customer needs and architecture determine the choice. For logic-to-logic connections in particular, he sees a strong case for chip-to-wafer assembly.

Patel asks how much more connection pitch can shrink. Osborn contrasts first-level interconnect pitches of roughly 130 to 150 micrometers fifteen years earlier with 25 micrometers in current high-volume Foveros production and sub-10-micrometer pitches in the work being discussed. He points to a paper at that year’s IEEE ECTC packaging conference reporting reliability data for a 0.45-micrometer-pitch hybrid-bonded device.

That leaves a substantial scaling runway. Osborn notes that the upper interconnect layers within a chip are around one micrometer to half a micrometer in scale. If packaging reaches 0.5 micrometers or below, designers can imagine connecting lower layers of one die more directly to lower layers of another, potentially removing some wiring layers and reducing voltage drop between transistor layers.

For AI, denser connections can improve access to memory bandwidth. Patel asks what the benefit is in applications where that particular advantage is less obvious. Osborn says companies are considering hybrid bonding for client devices as well: CPU-to-GPU connections can use the greater density, and finer interconnects can reduce the energy per transferred bit, measured in picojoules. Lower communication energy reduces the total system power budget and the heat needed for a given level of electrical performance.

The conversation now shifts from making better chips to making more of them. Patel asks Intel CTO Pushkar Ranade about an industry in which manufacturers depend on the same equipment suppliers. He cites ASML’s production of fewer than a hundred EUV machines a year and the competing claims on those tools from Intel, TSMC, and memory manufacturers such as SK hynix.

Ranade agrees that the equipment supply is a limit. Intel must make as much use as possible of installed capacity and increase output from its existing tool fleet. EUV is a particularly prominent bottleneck, but he says shortages extend across many other categories of semiconductor-manufacturing equipment as well.

Multiple suppliers in an equipment category do not automatically give a mature process flexibility. Once a flow such as 18A is established around a particular tool, Intel cannot simply substitute a different machine and expect the same process to work. The company remains dependent on the specific supplier and equipment it qualified. That makes the bottleneck more particular than the total number of machines available worldwide.

Patel asks how to preserve flexibility while defining 14A. Ranade says the general approach is to maintain as much reuse between generations as possible. As an illustrative figure, moving from 18A to 14A might allow reuse of 80% of the equipment set. Denser geometries still require some new capabilities and unique tools, but commonality makes a ramp less dependent on replacing everything.

Even unlimited capital cannot instantly overcome an installed-equipment limit. With a fixed footprint, Ranade sees incremental gains because mature processes already have high yields. Each additional percentage point becomes harder to obtain as the flow is fine-tuned. There is room to improve, but not an effortless order-of-magnitude expansion hidden inside existing operations.

Patel asks directly whether there are enough tools in the world for Intel to produce ten times as many leading-edge wafers. Ranade answers that tenfold is not possible with those constraints, but something like twice the output probably is. Patel contrasts that with AI compute growing roughly threefold annually over the preceding decade. Ranade says collective output cannot keep expanding unless the equipment makers, their suppliers, and their suppliers’ suppliers all produce more.

Patel offers a rough economic illustration: a few billion dollars of Intel capital expenditure might supply the logic for chips supporting around $100 billion of annual revenue at AI model companies. He acknowledges the other layers, including memory, that also contribute. His question is whether such demand and value creation should flow back into manufacturing commitments, with labs willing to guarantee future purchases to secure more supply.

Ranade says the demand signals are already exceptionally strong. He describes an industry that moved from vertical integration decades ago to a horizontal structure of foundries, equipment makers, and suppliers. Now hyperscalers design their own chips, and some customers could consume one fab’s output—or several—and have the capital to finance it. He sees a move toward virtual vertical integration, rather than a return to one company owning every step.

Patel asks how economies of scale operate when TSMC ships far more leading-edge wafers than Intel. Ranade calls foundries an especially pure example of scale economics. Building a fab creates such a large fixed-cost base that, in his estimate, around 80% of its cost structure is fixed. Every additional percentage point of utilization therefore matters greatly to the revenue the facility can support.

Intel fights for higher utilization and for more good output from the same equipment footprint. Ranade illustrates the latter with a die yield improving from 60% to 65% or 70%: more working chips emerge from an already costly factory. There is continuing economic value in that improvement. He connects the industry’s consolidation to these demands, contrasting the many manufacturers of earlier decades with only three remaining at advanced nodes.

Patel asks for Intel’s concrete plan to catch TSMC while leading-edge demand overflows into AI accelerators, CPUs, and other products. Ranade separates several meanings of catching up. In scale, TSMC is plainly much larger than Intel and Samsung, and closing that gap will be gradual rather than immediate.

On technology, Ranade argues that Intel is already competitive. He allows that performance, power, or area density may differ by a few percent, but distinguishes those gaps from being one or two entire generations behind. A full-generation difference has a clear effect on die area, output, and power; a small percentage difference is harder to reduce to a simple ranking.

A process is not a single-dimensional product. Different applications care about different combinations of density, speed, leakage, and other characteristics. Ranade puts particular emphasis on predictable timing, strong yields, and execution that supports a large and rapid production ramp. In his account, those factors can matter more than recovering a few percentage points on a headline performance or area metric.

Patel cites a SemiAnalysis density comparison suggesting that 14A, expected around 2028 in the discussion, might be comparable with TSMC’s N2. Ranade disputes the benchmark and returns to the importance of being broadly competitive and predictable. He does not accept density alone as a sufficient description of the technology.

Ranade points out that a node such as 14A or 18A includes several kinds of transistors, not one. There may be low-leakage devices, high-drive-current devices, high-density SRAM, high-performance SRAM, and analog or RF functions. The competitiveness of the process is the combination of those capabilities, judged against what a particular customer’s design requires.

Patel argues that equipment spending now becomes especially important if the tools purchased today determine who can serve future AI demand. He contrasts roughly $50 billion of TSMC capital expenditure with around $20 billion for Intel in the year being discussed. Ranade agrees that spending matters, but says the comparison is not entirely fair: TSMC serves the wider industry, while Intel still mainly manufactures for itself. He expects Intel’s capital expenditure to grow as its external foundry business grows.

Patel turns to Intel’s history in memory, from its DRAM origins to the later sale of its flash business, and asks how those exits look in the AI boom. Ranade says that, in hindsight, the timing of the flash sale was probably not ideal. He also says there were reasons for the decision then and that the enormous subsequent demand was not foreseeable.

Ranade now sees a world ready to absorb as much compute and memory as the industry can manufacture. He argues that the supply crunch in memory is even greater than the crunch in compute. The demand shock is therefore not confined to logic wafers or one kind of accelerator: several connected parts of the hardware supply chain must expand.

Patel summarizes a distinction between near-term surprises and the decade’s larger ceiling. Output might rise faster over twelve months than some expect, while the total expansion available by 2030 remains constrained. Ranade adds the essential condition: that ceiling can change if the whole supply chain ramps quickly. But an equipment order with an eighteen-month lead time already reaches toward 2028, and adding a new fab shell after that pushes the schedule toward the decade’s end.

Dwarkesh wants to discuss Intel’s partnership with Elon Musk on Terafab. What is going on there? Ranade notes that Elon has publicly talked about his desire to build a fab. In a clip, Musk says they either build the Terafab or they do not have the chips, and they need the chips, so they are going to build it. Same thinking, Ranade says: Musk is seeing an enormous increase in demand for silicon, compute and memory, and concluded his own businesses will require a lot of it. He thought maybe he should just do it on his own. Unlike building a car, this is so intricate that Intel thought they could work together to help accelerate bringing up his fab.

Dwarkesh pushes: because of the tool bottleneck, the net amount of silicon in the world will not increase. A new fab might just get guaranteed supply that it would not have as a foundry customer. Ranade says it is not just tools. A fab needs a lot of power, water, consumables; many other inputs. Dwarkesh says those can be scaled in a way tools cannot. Some more than others, Ranade agrees. They need a lot more equipment, but they also need a lot more raw fab space, raw cleanroom capacity.

If a foundry like Intel has to build these expensive facilities and buy expensive tools, what could the economics look like? Could it get more economical, scale faster? Ranade says this is an extremely capital-heavy business. Plot the cost to build a fab over 20, 30, 40 years and it is doubling every four to five years. Inside the fab, lithography — the most expensive module, just patterning — is doubling even faster. Today a High-NA EUV scanner and its associated equipment costs like $400 million.

If that rate continued, four years from now the cost of patterning would be like $800 million. That does not really make sense. A useful thought exercise: are there things that could be radically different today that they could not do 20 years ago? This is a very risk-averse industry for good reason. You put in tens of billions of dollars and you really do not want to take risks. You keep doing things the way they have been done for decades.

That is not just semiconductors; it is everything. Do it decade upon decade and you become indoctrinated. New engineers at Intel are taught this is how the fab works, this is the process flow, and they take that as gospel. Is that really the best way to build a chip today? It is a valid question. Dwarkesh wants to know what Ranade is hinting at: fewer litho passes to economize on the expensive component, or rethinking the transistor itself?

All of the above, Ranade says. The silicon transistor has evolved for 30 or 40 years and will continue: planar to FinFET to gate-all-around, and there will be more. That roadmap exists and is well defined. But there are other questions. Do you really need a cleanroom today? Does the infrastructure need to be as sophisticated and complex as it is?

Dwarkesh jokes that surely one can run an experiment with people eating hamburgers and smoking cigars in the research fab and see what happens to yield. Ranade says that would be a great experiment, but no incumbent — Intel, TSMC, Samsung — would willingly do it. That is what he meant: a very risk-averse business for good reason. Every day lost in productivity is who knows how many dollars.

Dwarkesh says you save so much money by not having to build cleanrooms in the future. Ranade comes back to the fear of the unknown. Nobody is going to willingly take that risk. Sometimes it is good to start with a clean slate and rethink everything. The same applies to chip design: many ways they do CPU design were probably locked in 30 years ago. Does that mean it is smart to still do it that way? Probably not. Chip design has more capacity to take risk; the fab has less. Given where the economics are today, maybe there is a smarter way to do this.

To close, Dwarkesh returns to the question they began with: how does Intel respond to this crazy AI demand that has already arrived? It sounds like if the ultimate bottleneck is tools from upstream, Intel ought to raise as much capital as possible right now. Nvidia has locked down memory and other components with reportedly hundreds of billions of dollars of commitments. Intel should maybe do the same, so that over the coming years the United States is in a good position to have the bulk of the most advanced semiconductor manufacturing happening here.

Ranade asks if Dwarkesh is suggesting they should be buying a lot more tools. Yes, Dwarkesh says, because otherwise in a couple of years you are in a position where you could be making trillions of dollars and all the tools are in Taiwan. Ranade says that is a very valid question. Had they known what they know today, they would have invested more like a year ago. Knowing what they know now, he thinks they will be investing more.